The multilayer printed wiring board includes a build-up multilayer printed wiring board in which conductor circuitry layers and insulative resin layers are alternately formed one on another and inner and outer ones of the conductor circuitry layers are electrically connected to each other by viaholes formed in the insulative resin layers. Generally, the viaholes in such a multilayer printed wiring board are formed by depositing a plating metal film on the inner wall and bottom of each of fine holes formed through the interlaminar insulative resin layers.
However, the multilayer printed wiring board having such viaholes formed through them are not advantageous in that the metal deposit is likely to break due to its precipitation or a heat cycle. To avoid this problem, it has recently been proposed to fill the viaholes with a plating metal (this structure will be referred to as “filled viahole structure” henceforth). Such filled viahole structures are known from the disclosure, for example, in the Japanese unexamined patent publication Nos. Hei 2-188992, Hei 3-3298 and Hei 7-34048.
The multilayer printed wiring board having the filled viahole structure is however disadvantageous in that a surface portion of the plating metal exposed outside the hole for viahole (the surface will be referred to as “viahole surface” henceforth) is easily depressible. If an interlaminar resin insulating layer is formed on a conductor circuitry layer irrespectively of such a depression existent on the viahole surface, a corresponding depression will develop on the surface of the interlaminar insulative resin layer, and cause the plating metal film to break and also a trouble in mounting electronic parts on the wiring board.
The viahole surface where such a depression or concavity exists or is likely to exist can be flattened by applying an interlaminar resin more than once. However, the application of the interlaminar resin will lead to a greater thickness of the interlaminar insulative resin layer just above the depression on the viahole surface than that of the interlaminar insulative resin layer on the conductor circuitry layer. Thus in the process of forming a hole for a viahole in the interlaminar insulative resin layer by exposure, development and laser radiation, the interlaminar resin will partially remain in side the hole to lower the electrical connection reliability of the viahole. Especially for mass production of multilayer printed wiring boards, the residual resin is likely to occur since it is difficult to set different exposure and development conditions for the viahole surface from those for the conductor circuitry layer surface.
Further, to solve the problem of such a residual resin, a build-up multilayer printed wiring board has been proposed by the Japanese unexamined patent publication No. Hei 9-312472, etc.
In this conventional multilayer printed wiring board, a plating conductor or metal is filled in a hole for viahole so that a conductor circuitry layer has a thickness more than a half of the viahole diameter and thus the conductor circuitry layer surface is at a same level as the viahole surface.
In this conventional multilayer printed wiring board, however, the inner wall of the hole formed in an interlaminar insulative resin layer should be plated with a thick layer of metal or conductor and thus a conductor circuitry layer formed along with the plating metal on the viahole will also be thick.
For a thicker plating, the plating resin should also be correspondingly thicker. As a result, light will de diffracted to inside a pattern on a photomasking film, so that the plating resist will be taper. That is, there will be resulted a conductor pattern which is thinner as it goes downward. Such a phenomenon will not matter so long as L/S=50/50 μm where L: line width; S: inter-line distance, but it will cause a pattern separation (peeling) if the pattern is a fine one of L/S=25/25 μm.
Further, as disclosed in the Japanese unexamined patent publication No. Hei 2-188992, when a plating layer is formed and then it is etched to form a conductor circuitry layer, a thick plating layer will be undercut due to the etching and a fine pattern will be broken.
Furthermore, since in the filled viahole structure, a plating metal is filled in a hole for viahole, a larger stress will be caused by heat cycle than in a viahole formed just by plating an inner wall and bottom of a hole, so that a crack is likely to occur first in the viahole and then spread to an interlaminar insulative resin layer.
Moreover, an electroless plating method is used to fill the plating metal into the hole for viahole. However, the plating layer applied by the electroless plating is harder and less malleable than a one applied by the electroplating. Therefore, the plating layer is likely to crack under a thermal shock or due to heat cycle.
To solve the above problem, a method of forming a filled viahole structure by using both electroless plating and electroplating has been proposed as disclosed in the Japanese unexamined patent publication No. Hei 9-312472.
In this filled viahole structure, however, the boundary between the electroless plating and electroplating layers is flat so that both the plating layers are separable from each other under a thermal shock or due to heat cycle. To avoid this separation, a plating resist has to be formed before a hole for viahole is filled with a metal by the electroplating. However, since the plating resist is formed on the electroless plating layer, the plating resist is easily separable and an inter-pattern short circuit will possibly take place.
Accordingly, the present invention has a primary object to overcome the above-mentioned drawbacks of the prior art by providing a multilayer printed wiring board having a filled viahole structure adapted to form a fine conductor circuit pattern and provide a highly reliable electrical connection between conductive circuitry layers.
The present invention has another object to provide a multilayer printed wiring board having a filled viahole structure adapted to assure a highly secure adhesion between a conductor circuitry layer and an interlaminar insulative resin layer and which will not crack even under a thermal shock or due to heat cycle.